SST89E516RD-40-C-PIE

Product Summary

The SST89E516RD-40-C-PIE is an 8-bit microcontroller. It is designed and manufactured with SST’s patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for SST’s customers. The SST89E516RD-40-C-PIE uses the 8051 instruction set and is pin-for-pin compatible with standard 8051 microcontroller devices. The SST89E516RD-40-C-PIE is pre-programmed with an example of the bootstrap loader in the memory, demonstrating the initial user program code loading or subsequent user code updating via the IAP operation.

Parametrics

SST89E516RD-40-C-PIE absolute maximum ratings: (1)Ambient Temperature Under Bias:-55℃ to +125℃; (2)Storage Temperature:-65℃ to +150℃; (3)Voltage on EA# Pin to VSS:-0.5V to +14.0V; (4)D.C. Voltage on Any Pin to Ground Potential:-0.5V to VDD+0.5V; (5)Transient Voltage (<20ns) on Any Other Pin to VSS:-1.0V to VDD+1.0V; (6)Maximum IOL per I/O Pins P1.5, P1.6, P1.7:20mA; (7)Maximum IOL per I/O for All Other Pins:15mA; (8)Package Power Dissipation Capability (TA = 25℃):1.5W; (9)Through Hole Lead Soldering Temperature (10 Seconds):300℃; (10)Surface Mount Solder Reflow Temperature1:260℃ for 10 seconds; (11)Output Short Circuit Current:50 mA.

Features

SST89E516RD-40-C-PIE features: (1)Fully Software Compatible; (2)Development Toolset Compatible; (3)Pin-For-Pin Package Compatible; (4)64 KByte primary block + 8 KByte secondary block (128-Byte sector size for both blocks); (5)Individual Block Security Lock with SoftLock; (6)Concurrent Operation during In-Application Programming (IAP); (7)Memory Overlay for Interrupt Support during IAP; (8)Support External Address Range up to 64 KByte of Program and Data Memory; (9)Three High-Current Drive Ports (16 mA each); (10)Three 16-bit Timers/Counters; (11)Full-Duplex, Enhanced UART; (12)Ten Interrupt Sources at 4 Priority Levels: Four External Interrupt Inputs; (13)Programmable Watchdog Timer (WDT); (14)Programmable Counter Array (PCA); (15)Four 8-bit I/O Ports (32 I/O Pins) and One 4-bit Port; (16)Second DPTR register; (17)Low EMI Mode (Inhibit ALE); (18)SPI Serial Interface; (19)Standard 12 Clocks per cycle, the device has an option to double the speed to 6 clocks per cycle; (20)TTL- and CMOS-Compatible Logic Levels; (21)Brown-out Detection; (22)Low Power Modes.

Diagrams